1. Field of the Invention
The present invention is related to the field of data communications, and more specifically towards systems, circuits, and methods for phase inversion of a clock signal.
2. Art Background
Electronic circuits utilize serial data transmission to transmit data among one or more circuits. In general, serial data transmission involves transmitting bits in a single bit stream at a predetermined data rate. The data rate is expressed as the number of bits transmitted per second (“bps”). Typically, to transfer data between circuits, the sending circuit employs a transmitter that modulates and sends data using a local clock. The local clock provides the timing for the bit rate. The receiving circuit employs a receiver to recover the data, and in some cases, the clock. The receiver circuit recovers the serial bit stream of data by sampling the bit stream at the specified data rate.
Techniques have been developed in an attempt to optimize the timing performance of circuits receiving data and clock signals. For example, flip-flops or memory components of a receiving circuit may be constrained by setup time and hold time violations. Setup time is the minimum amount of time that the data signal should be held steady before a clock event such that the data is reliably sampled by the clock. Hold time is the minimum amount of time that the data signal should be held steady after the clock event such that the data is reliably sampled. Both setup time and hold time are important design considerations with respect to synchronous circuits such as flip flops that receive a clock signal. A setup time violation or a hold time violation may result in unstable or unreliable data.
Techniques have been developed to adjust the data signal in order to optimize the timing performance parameters of circuits. For example, buffers or delays may be inserted to adjust the delay of data signals to address setup time violations and/or hold time violations. However, it is also advantageous to be able to adjust or adapt the clock signal in order to optimize the timing performance of a circuit. For example, in some systems, the clock signal may be subject to clock skew, or timing skew, where a clock signal arrives at different components in a synchronous circuit at different times. This may be caused by differences in wire interconnect length, temperature variations, capacitive coupling, and material imperfections or defects.
Accordingly, it is highly desirable to develop systems, circuits and methods for adjusting a clock signal. For example, it is highly desirable to address phase differences between clock signals in order to improve the timing performance of a circuit.